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#define | BIT31 0x80000000 |
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#define | BIT30 0x40000000 |
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#define | BIT29 0x20000000 |
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#define | BIT28 0x10000000 |
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#define | BIT27 0x08000000 |
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#define | BIT26 0x04000000 |
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#define | BIT25 0x02000000 |
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#define | BIT24 0x01000000 |
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#define | BIT23 0x00800000 |
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#define | BIT22 0x00400000 |
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#define | BIT21 0x00200000 |
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#define | BIT20 0x00100000 |
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#define | BIT19 0x00080000 |
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#define | BIT18 0x00040000 |
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#define | BIT17 0x00020000 |
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#define | BIT16 0x00010000 |
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#define | BIT15 0x00008000 |
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#define | BIT14 0x00004000 |
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#define | BIT13 0x00002000 |
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#define | BIT12 0x00001000 |
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#define | BIT11 0x00000800 |
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#define | BIT10 0x00000400 |
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#define | BIT9 0x00000200 |
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#define | BIT8 0x00000100 |
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#define | BIT7 0x00000080 |
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#define | BIT6 0x00000040 |
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#define | BIT5 0x00000020 |
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#define | BIT4 0x00000010 |
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#define | BIT3 0x00000008 |
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#define | BIT2 0x00000004 |
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#define | BIT1 0x00000002 |
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#define | BIT0 0x00000001 |
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#define | ETS_UNCACHED_ADDR(addr) (addr) |
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#define | ETS_CACHED_ADDR(addr) (addr) |
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#define | READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) |
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#define | WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val) |
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#define | CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))) |
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#define | SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))) |
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#define | GET_PERI_REG_BITS(reg, hipos, lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)) |
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#define | SET_PERI_REG_BITS(reg, bit_map, value, shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|((value)<<(shift)) )) |
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#define | APB_CLK_FREQ 80*1000000 |
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#define | UART_CLK_FREQ APB_CLK_FREQ |
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#define | TIMER_CLK_FREQ (APB_CLK_FREQ>>8) |
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#define | PERIPHS_DPORT_BASEADDR 0x3ff00000 |
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#define | PERIPHS_GPIO_BASEADDR 0x60000300 |
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#define | PERIPHS_TIMER_BASEDDR 0x60000600 |
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#define | PERIPHS_RTC_BASEADDR 0x60000700 |
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#define | PERIPHS_IO_MUX 0x60000800 |
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#define | EDGE_INT_ENABLE_REG (PERIPHS_DPORT_BASEADDR+0x04) |
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#define | TM1_EDGE_INT_ENABLE() SET_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT1) |
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#define | TM1_EDGE_INT_DISABLE() CLEAR_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT1) |
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#define | GPIO_REG_READ(reg) READ_PERI_REG(PERIPHS_GPIO_BASEADDR + reg) |
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#define | GPIO_REG_WRITE(reg, val) WRITE_PERI_REG(PERIPHS_GPIO_BASEADDR + reg, val) |
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#define | GPIO_OUT_ADDRESS 0x00 |
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#define | GPIO_OUT_W1TS_ADDRESS 0x04 |
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#define | GPIO_OUT_W1TC_ADDRESS 0x08 |
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#define | GPIO_ENABLE_ADDRESS 0x0c |
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#define | GPIO_ENABLE_W1TS_ADDRESS 0x10 |
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#define | GPIO_ENABLE_W1TC_ADDRESS 0x14 |
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#define | GPIO_OUT_W1TC_DATA_MASK 0x0000ffff |
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#define | GPIO_IN_ADDRESS 0x18 |
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#define | GPIO_STATUS_ADDRESS 0x1c |
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#define | GPIO_STATUS_W1TS_ADDRESS 0x20 |
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#define | GPIO_STATUS_W1TC_ADDRESS 0x24 |
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#define | GPIO_STATUS_INTERRUPT_MASK 0x0000ffff |
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#define | GPIO_RTC_CALIB_SYNC PERIPHS_GPIO_BASEADDR+0x6c |
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#define | RTC_CALIB_START BIT31 |
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#define | RTC_PERIOD_NUM_MASK 0x3ff |
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#define | GPIO_RTC_CALIB_VALUE PERIPHS_GPIO_BASEADDR+0x70 |
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#define | RTC_CALIB_RDY_S 31 |
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#define | RTC_CALIB_VALUE_MASK 0xfffff |
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#define | GPIO_PIN0_ADDRESS 0x28 |
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#define | GPIO_ID_PIN0 0 |
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#define | GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n)) |
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#define | GPIO_LAST_REGISTER_ID GPIO_ID_PIN(15) |
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#define | GPIO_ID_NONE 0xffffffff |
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#define | GPIO_PIN_COUNT 16 |
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#define | GPIO_PIN_CONFIG_MSB 12 |
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#define | GPIO_PIN_CONFIG_LSB 11 |
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#define | GPIO_PIN_CONFIG_MASK 0x00001800 |
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#define | GPIO_PIN_CONFIG_GET(x) (((x) & GPIO_PIN_CONFIG_MASK) >> GPIO_PIN_CONFIG_LSB) |
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#define | GPIO_PIN_CONFIG_SET(x) (((x) << GPIO_PIN_CONFIG_LSB) & GPIO_PIN_CONFIG_MASK) |
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#define | GPIO_WAKEUP_ENABLE 1 |
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#define | GPIO_WAKEUP_DISABLE (~GPIO_WAKEUP_ENABLE) |
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#define | GPIO_PIN_WAKEUP_ENABLE_MSB 10 |
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#define | GPIO_PIN_WAKEUP_ENABLE_LSB 10 |
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#define | GPIO_PIN_WAKEUP_ENABLE_MASK 0x00000400 |
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#define | GPIO_PIN_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN_WAKEUP_ENABLE_MASK) >> GPIO_PIN_WAKEUP_ENABLE_LSB) |
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#define | GPIO_PIN_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN_WAKEUP_ENABLE_LSB) & GPIO_PIN_WAKEUP_ENABLE_MASK) |
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#define | GPIO_PIN_INT_TYPE_MASK 0x380 |
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#define | GPIO_PIN_INT_TYPE_MSB 9 |
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#define | GPIO_PIN_INT_TYPE_LSB 7 |
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#define | GPIO_PIN_INT_TYPE_GET(x) (((x) & GPIO_PIN_INT_TYPE_MASK) >> GPIO_PIN_INT_TYPE_LSB) |
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#define | GPIO_PIN_INT_TYPE_SET(x) (((x) << GPIO_PIN_INT_TYPE_LSB) & GPIO_PIN_INT_TYPE_MASK) |
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#define | GPIO_PAD_DRIVER_ENABLE 1 |
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#define | GPIO_PAD_DRIVER_DISABLE (~GPIO_PAD_DRIVER_ENABLE) |
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#define | GPIO_PIN_PAD_DRIVER_MSB 2 |
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#define | GPIO_PIN_PAD_DRIVER_LSB 2 |
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#define | GPIO_PIN_PAD_DRIVER_MASK 0x00000004 |
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#define | GPIO_PIN_PAD_DRIVER_GET(x) (((x) & GPIO_PIN_PAD_DRIVER_MASK) >> GPIO_PIN_PAD_DRIVER_LSB) |
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#define | GPIO_PIN_PAD_DRIVER_SET(x) (((x) << GPIO_PIN_PAD_DRIVER_LSB) & GPIO_PIN_PAD_DRIVER_MASK) |
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#define | GPIO_AS_PIN_SOURCE 0 |
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#define | SIGMA_AS_PIN_SOURCE (~GPIO_AS_PIN_SOURCE) |
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#define | GPIO_PIN_SOURCE_MSB 0 |
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#define | GPIO_PIN_SOURCE_LSB 0 |
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#define | GPIO_PIN_SOURCE_MASK 0x00000001 |
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#define | GPIO_PIN_SOURCE_GET(x) (((x) & GPIO_PIN_SOURCE_MASK) >> GPIO_PIN_SOURCE_LSB) |
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#define | GPIO_PIN_SOURCE_SET(x) (((x) << GPIO_PIN_SOURCE_LSB) & GPIO_PIN_SOURCE_MASK) |
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#define | RTC_REG_READ(addr) READ_PERI_REG(PERIPHS_TIMER_BASEDDR + addr) |
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#define | RTC_REG_WRITE(addr, val) WRITE_PERI_REG(PERIPHS_TIMER_BASEDDR + addr, val) |
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#define | RTC_CLR_REG_MASK(reg, mask) CLEAR_PERI_REG_MASK(PERIPHS_TIMER_BASEDDR +reg, mask) |
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#define | NOW() RTC_REG_READ(FRC2_COUNT_ADDRESS) |
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#define | FRC1_LOAD_ADDRESS 0x00 |
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#define | FRC1_COUNT_ADDRESS 0x04 |
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#define | FRC1_CTRL_ADDRESS 0x08 |
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#define | FRC1_INT_ADDRESS 0x0c |
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#define | FRC1_INT_CLR_MASK 0x00000001 |
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#define | FRC2_COUNT_ADDRESS 0x24 |
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#define | REG_RTC_BASE PERIPHS_RTC_BASEADDR |
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#define | RTC_STORE0 (REG_RTC_BASE + 0x030) |
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#define | RTC_STORE1 (REG_RTC_BASE + 0x034) |
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#define | RTC_STORE2 (REG_RTC_BASE + 0x038) |
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#define | RTC_STORE3 (REG_RTC_BASE + 0x03C) |
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#define | RTC_GPIO_OUT (REG_RTC_BASE + 0x068) |
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#define | RTC_GPIO_ENABLE (REG_RTC_BASE + 0x074) |
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#define | RTC_GPIO_IN_DATA (REG_RTC_BASE + 0x08C) |
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#define | RTC_GPIO_CONF (REG_RTC_BASE + 0x090) |
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#define | PAD_XPD_DCDC_CONF (REG_RTC_BASE + 0x0A0) |
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#define | PERIPHS_IO_MUX_FUNC 0x13 |
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#define | PERIPHS_IO_MUX_FUNC_S 4 |
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#define | PERIPHS_IO_MUX_PULLUP BIT7 |
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#define | PERIPHS_IO_MUX_PULLUP2 BIT6 |
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#define | PERIPHS_IO_MUX_SLEEP_PULLUP BIT3 |
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#define | PERIPHS_IO_MUX_SLEEP_PULLUP2 BIT2 |
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#define | PERIPHS_IO_MUX_SLEEP_OE BIT1 |
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#define | PERIPHS_IO_MUX_OE BIT0 |
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#define | PERIPHS_IO_MUX_CONF_U (PERIPHS_IO_MUX + 0x00) |
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#define | SPI0_CLK_EQU_SYS_CLK BIT8 |
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#define | SPI1_CLK_EQU_SYS_CLK BIT9 |
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#define | PERIPHS_IO_MUX_MTDI_U (PERIPHS_IO_MUX + 0x04) |
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#define | FUNC_GPIO12 3 |
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#define | PERIPHS_IO_MUX_MTCK_U (PERIPHS_IO_MUX + 0x08) |
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#define | FUNC_GPIO13 3 |
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#define | PERIPHS_IO_MUX_MTMS_U (PERIPHS_IO_MUX + 0x0C) |
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#define | FUNC_GPIO14 3 |
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#define | PERIPHS_IO_MUX_MTDO_U (PERIPHS_IO_MUX + 0x10) |
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#define | FUNC_GPIO15 3 |
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#define | FUNC_U0RTS 4 |
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#define | PERIPHS_IO_MUX_U0RXD_U (PERIPHS_IO_MUX + 0x14) |
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#define | FUNC_GPIO3 3 |
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#define | PERIPHS_IO_MUX_U0TXD_U (PERIPHS_IO_MUX + 0x18) |
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#define | FUNC_U0TXD 0 |
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#define | FUNC_GPIO1 3 |
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#define | PERIPHS_IO_MUX_SD_CLK_U (PERIPHS_IO_MUX + 0x1c) |
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#define | FUNC_SDCLK 0 |
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#define | FUNC_SPICLK 1 |
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#define | PERIPHS_IO_MUX_SD_DATA0_U (PERIPHS_IO_MUX + 0x20) |
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#define | FUNC_SDDATA0 0 |
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#define | FUNC_SPIQ 1 |
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#define | FUNC_U1TXD 4 |
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#define | PERIPHS_IO_MUX_SD_DATA1_U (PERIPHS_IO_MUX + 0x24) |
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#define | FUNC_SDDATA1 0 |
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#define | FUNC_SPID 1 |
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#define | FUNC_U1RXD 4 |
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#define | FUNC_SDDATA1_U1RXD 7 |
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#define | PERIPHS_IO_MUX_SD_DATA2_U (PERIPHS_IO_MUX + 0x28) |
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#define | FUNC_SDDATA2 0 |
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#define | FUNC_SPIHD 1 |
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#define | FUNC_GPIO9 3 |
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#define | PERIPHS_IO_MUX_SD_DATA3_U (PERIPHS_IO_MUX + 0x2c) |
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#define | FUNC_SDDATA3 0 |
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#define | FUNC_SPIWP 1 |
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#define | FUNC_GPIO10 3 |
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#define | PERIPHS_IO_MUX_SD_CMD_U (PERIPHS_IO_MUX + 0x30) |
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#define | FUNC_SDCMD 0 |
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#define | FUNC_SPICS0 1 |
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#define | PERIPHS_IO_MUX_GPIO0_U (PERIPHS_IO_MUX + 0x34) |
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#define | FUNC_GPIO0 0 |
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#define | PERIPHS_IO_MUX_GPIO2_U (PERIPHS_IO_MUX + 0x38) |
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#define | FUNC_GPIO2 0 |
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#define | FUNC_U1TXD_BK 2 |
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#define | FUNC_U0TXD_BK 4 |
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#define | PERIPHS_IO_MUX_GPIO4_U (PERIPHS_IO_MUX + 0x3C) |
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#define | FUNC_GPIO4 0 |
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#define | PERIPHS_IO_MUX_GPIO5_U (PERIPHS_IO_MUX + 0x40) |
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#define | FUNC_GPIO5 0 |
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#define | PIN_PULLUP_DIS(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME, PERIPHS_IO_MUX_PULLUP) |
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#define | PIN_PULLUP_EN(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME, PERIPHS_IO_MUX_PULLUP) |
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#define | PIN_FUNC_SELECT(PIN_NAME, FUNC) |
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